`timescale 1ns / 1ps
/******************************************************************************
*                                                                             *
* UTICA softcore v0.1                                                         *
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* Copyright (c) 2012 Andrew D. Zonenberg                                      *
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/**
	@file IPv4ArpCache.v
	@author Andrew D. Zonenberg
	@brief IPv4 ARP cache
	
	Direct mapped, 256 entries.
	
	Single ported - can perform one read or one write per clock, but not both.
 */
module IPv4ArpCache(
	clk,
	ip_addr, mac_in, wr,
	mac_out, cache_hit
    );
	 
	///////////////////////////////////////////////////////////////////////////////////////////////
	// IO declarations
	input wire clk;
	 
	input wire[31:0] ip_addr;
	input wire[47:0] mac_in;
	input wire wr;
	
	output wire[47:0] mac_out;
	output wire cache_hit;
	 
	///////////////////////////////////////////////////////////////////////////////////////////////
	// The actual memory array
	 
	wire[23:0] ip_high_out;
	BlockRamDualWidthMacro arp_table (
		.clk(clk), 
		.addr(ip_addr[7:0]), 
		.we(wr), 
		.din({ip_addr[31:8], mac_in}), 
		.dout({ip_high_out, mac_out})
		);

	wire valid;
	RAM256X1S #(
		.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000)
	) valid_table (
		.O(valid),
		.A(ip_addr[7:0]),
		.WE(wr),
		.WCLK(clk),
		.D(1'b1)
	);	 
	
	reg[23:0] ip_high_buf = 0;
	reg valid_buf = 0;
	always @(posedge clk) begin
		ip_high_buf <= ip_addr[31:8];
		valid_buf <= valid;
	end
	
	assign cache_hit = (ip_high_buf == ip_high_out) && valid_buf;

endmodule
